Job ID: AnG – 1056
PFB the requirement details:-
– Experienced ASIC Verification engineer responsible for implementing and executing verification plan to verify DDR memory Controller/PHY features.
– Requires a strong background in digital verification from planning to coverage closure.
– Previous experience designing configurable IP is a strong plus.
– Experience in verification using SV/UVM at IP level.
– Knowledge of DDR memory protocol
– Knowledge of Python or Perl for scripting
– Experience with highly configurable designs