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Job ID: AnG – 1056

 

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PFB the requirement details:-

– Experienced ASIC Verification engineer responsible for implementing and executing verification plan to verify DDR memory Controller/PHY features.

– Requires a strong background in digital verification from planning to coverage closure.

– Previous experience designing configurable IP is a strong plus.

– Experience in verification using SV/UVM at IP level.

Desired skills:

– Knowledge of DDR memory protocol

– Knowledge of Python or Perl for scripting

– Experience with highly configurable designs

 

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