RTL Design- Bangalore- 4-15 years

Job Summary: We are looking for talented RTL Engineers and Leads with expertise in High-speed IPs and CPUs. The ideal candidate will have over 4 years and above experience in uArch design, RTL coding, quality checks (Linting, CDC, Synthesis) and integration of High-speed IPs/CPUs in complex ASICs/SoC s. Key Responsibilities:
•Micro architecture design
•Develop RTL design/coding for ASIC and SoC projects.
•Collaborate closely with architects and physical design teams to achieve design goals.
•Optimize RTL designs for performance, power, and area (PPA) metrics.
•Participate in design reviews and contribute to the overall design methodologyimprovements.
•Integration of High-speed IPs (Controller, Phy)
•Support post-silicon validation and debug activities as needed.
Qualifications:
•4-15 years of hands-on experience in RTL design, Integration with High-speed IPs.
•Proficiency in Verilog/System Verilog/Chisel coding and familiarity with RTL simulationtools (e.g., Questa, VCS).
•Solid understanding of ASIC and SoC design flows and methodologies.
•Good experience and knowledge in integrating one or more of the following high-speedIPs/Interfaces is must. The Highspeed IPs, Interfaces include DDR (LPDDR 4/5/6, GDDR6),PCIe Gen 4/5/6, CXL 2/3, UCIe, Ethernet 100G/200G/400G/800G, Coherent Interconnectslike ARM CMN, CPUs like ARM Cortex X4, A7xx, A5xx, A7x, A5x series, Neoverse N2
•Good knowledge in one or more of the following protocols/specifications is must. Theprotocols/specifications include PCIe Gen4/5/6, CXL 2/3, UCIe, Ethernet, AMBA CHI
•Good experience and knowledge in Linting, CDC and Synthesis
•Good knowledge in clocking, reset and power.
•Experience with linting, CDC, synthesis and timing analysis tools (e.g., Synopsys spyglass,DC).
•Strong analytical and problem-solving skills.
•Excellent communication and teamwork abilities.